Design for Manufacturability
REV. A DFM Checklist
Customer Name: Receive Date:
Product Name: Start Date:
Assembly No/Rev: Delivery Date:
Findings are rated as follows
Hot- Strongly recommended; Medium – Recommended; Cold – Not necessary but nice to have; Post assembly report only.
* Is the Workmanship Standard IPC-A-610, Class II? Yes ( ) No ( ), then it is ___________________
Section I:
Incoming PCBA Checklist
Status Ok?
Description Yes No Explanation: Include hyperlinks to pictures and/or recommendations
Documentation CAD / Gerber
1 Centroid data, part orientation (Sufficient/ editing required)
2 CAD Database provided with Gerber and minimum manual editing
3 Reference designator available and not encroaching or overlaping features
4 Fiducial Co-ordinates available in CAD /centroid data
5 Package type available for each part?
6 Dimensional information available for all critical parts (preferably datasheets)
7 Mismatch between CAD/BOMProgram Checked Out?
8 Fabrication / Assembly Drawing (Display Sufficient Information and are accurate)
9 BOM Description (Should contain the value, part marking, and the correct package shape)
Material Handling and Panel Design
10 Board size (Max. 457.2x508mm/18"X20"; Min. 50.8x101.6mm/ 2"X4" )
11 Board thickness (Max: 3.175mm/0.125"; Min: 0.8128mm/0.032");
12 Board shape (square, or rectangular, or others)
13 Break away designed (to minimize material waste, to make PCB square or rectangular)?
14 Panelization tab is strong for process
15 Breakout tab (type: shear/scored/router/mousebite, V-groove, and the location)
16 Panel Warpage during Processing (7 mils per inch or 40 mils/1.016mm, whichever is minimum)
PCB Design
17 Layer Stackup (Balanced)
18 PCB fab coating (improper coating, contamination, trace cut)
19 PCB fab surface finish (Tin/Lead over copper if no fine pitch component, Gold/Nickel for fine pitch components and BGAs)
20 Silk screen (legible, polarity, outline & not on pad)
21 Polarity (defined correctly, missing)?
22 Global fiducial marks (Non-plated, 1.016mm/0.040"dia.; mask free, 3.048mm/0.120"dia.; No. & locations)
23 Local fiducial on QFP locations (Non-plated, 1.016mm/0.040"dia.; mask free, 3.048mm/0.120"dia.)
24 Solder Mask (clearance around fine pitch, alignment)?
Pad Design
25 QFP footprint meets std (std: toe & heel's pad > 0.254mm/ 0.01")
26 PLCC footprint meets std (std: toe & heel's pad > 0.254mm/0.01", pad size: 0.635x2.54mm/0.025"x0.100")
27 BGA - Proper pad geometry
28 Land pattern (proper sizes for wave/reflow)
29 Plated Through Hole Design (enough clearance between the lead and the PTH for easy insertion and good solder joint)
30 Others
Component Issues
31 Spacing between chips (std: x/y >/= 0.5mm/0.0197")
32 Spacing for <0.635mm/25 mil fine pitch (min. 2mm/0.0787")
33 Component population (even distribution, consistent & proper orientation for wave/reflow)
34 BGA Spacing
35 Orientation for Placement
36 Orientation and Spacing for Wave Soldering
37 Components matching the respective pad size
38 Component Distribution for thermal mass mgmt.
39 Proximity of SMT components to the Through Pins on the other side
Tooling Holes
40 Tooling hole size (std:3.175mm/ 0.125"); Tolerance +0.0254mm/-0.0000mm (+0.001"/-0.000")
41 Tooling hole location (std: Y=5.08mm/0.2", normal:5.08mm/0.200" from low-right corners, both edges); 2 ea. Diagonal locations
42 Via hole (open 100% or partially covered by solder mask); All Vias should be closed to prevent vacuum leak.
43 Via hole location (0.318mm/0.015" dia size Min.; Not directly next to pad, 0.254mm/0.010" Min. w/trace; Not underneath part); BGA vias should have a minimum of 0.3048mm/0.012" solder dams
44 Board edge clearance (min 3mm/0.118" )
Comments:___________________________________________________________________________________________
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Section II:
Component and Packaging
Status Ok?
Description Yes No Explanation: Include hyperlinks to pictures and/or recommendations
1 SMD component (on tape & reel when possible)
2 SMD Comp. for automation when possible
3 SMD comp. right size, right tolerance
4 SMD comp. no oxidation, improper coating
Comments:___________________________________________________________________________________________
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Section III:
Process Issues
Status Ok?
Description Yes No Explanation: Include hyperlinks to pictures and/or recommendations
1 Solder Paste used
2 Stencil
3 Placement Machine
4 Reflow Oven
5 Wave Soldering
Comments:___________________________________________________________________________________________
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Section IV:
Supporting Information and Digital PICs
Prepared by: ____________________________ Title: Proj Engr. Date: _________________
Approved by: ___________________________ Title: Engr. Mgr. Date: _________________
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