library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dl_control is
port (
--时钟输入
clk : in std_logic ;
--安锁
lock : in std_logic ;
--输入
密码 start : in std_logic;
--报警复位
off_al : in std_logic;
--修改密码
ps_ch : in std_logic;
--密码确认
enter : in std_logic;
--密码脉冲
ps_i : in std_logic;
-- 比较结果
cmp_r : in std_logic;
--完成密码输入指示
cin : in std_logic;
--密码输入使能
code_en : out std_logic;
--计数器清零
cnt_clr :out std_logic;
--计数器时钟
cnt_clk : out std_logic ;
--寄存器读/写信号
reg_wr : out std_logic;
--钥匙信号
key : out std_logic;
--报警信号
warn :out std_logic
);
end dl_control;
architecture behave of dl_control is
--常量定义
constant key_active : std_logic :='1';
--状态机定义
--共7个状态,分别是:开锁,安锁,输入密码,密码初验正确,密码初验
--错误,报警及修改密码
type state_type is (outlock,inlock,ps_input,ps_right,ps_wrong,alarm,ps_change);
signal state : state_type;
begin
--密码麻脉冲作为计数时钟
cnt_clk <= ps_i;
----------
--状态机
----------
process(clk)
begin
if rising_edge(clk) then
case state is
--开锁状态
when outlock =>
--开锁
key<='0';
if lock = key_active then
state<= inlock ;
elsif ps_ch = key_active then
state<= ps_change;
else
state<= outlock ;
end if;
--安锁状态
when inlock =>
-- 关锁
key <='1';
--禁止输入密码
code_en <= '0';
--清零计数器
cnt_clr <='1';
reg_wr <='0';
warn <='0';
if start = key_active then
state <= ps_input;
else
state <= inlock ;
end if ;
--输入密码状态
when ps_input =>
--允许输入密码
code_en <= '1';
cnt_clr <='0';
--寄存器读使能
reg_wr <='0';
--密码位数和内容均正确
if cin='1' and ps_i ='1'and cmp_r='1' then
code_en <= '0';
cnt_clr <= '1';
state <= ps_right;
--密码出现错误
elsif ps_i ='1'and cmp_r='0' then
code_en <= '0';
cnt_clr <= '1';
state <= ps_wrong;
-- 在密码位数不足时,按enter键,则直接报警
elsif enter = key_active and cin = '0' then
code_en <= '0';
cnt_clr <= '1';
state <= alarm;
else
state <= ps_input;
end if;
--密码初验正确状态
when ps_right =>
if enter = key_active then
state <= outlock;
else
state <=ps_right;
end if ;
--密码初验错误状态
when ps_wrong =>
if enter = key_active then
state <=alarm;
else
state <= ps_wrong;
end if ;
--报警状态
when alarm =>
if off_al = key_active then
warn <= '0';
state <= inlock;
else
warn <= '1';
state <= alarm;
end if;
--修改密码状态
when ps_change =>
--允许输入密码
code_en <= '1';
cnt_clr <='0';
--寄存器写使能
reg_wr <='1';
--计数满且密码正确
if cin='1' then
code_en <='0';
cnt_clr <= '1';
state <= outlock;
end if ;
when others =>
state <= inlock;
end case ;
end if ;
end process;
end behave;
为什么 不管clk 是什么 state 都是 1啊 在quartus 仿真的